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Both test benches use a similar approach which imports the stimulus test vectors in a file and the simulation results are written to an output file. The gate-level simulation test bench compares the expected responses with actual responses from the circuit and outputs error messages if they do not match. This file contains not only the stimulus, but also the expected responses. Each line of the file consists of one vector of stimulus data that the VHDL test bench reads.
Since this is a very simple circuit, there is no expected output included in the test vector generation program. Since the CMC digital tutorial contains a step by step 74sl165 of how to use the Test Fixturing Software, a description will not be given here.
The functional test vectors are generated with a simple C program lstv. The test bench uses a clock to output the stimulus data in a periodic manner. After gate-level simulation, the design can be exported to Cadence to finish the rest 74ps165 the design flow as described in the Design Flow section.
Synopsys is used to synthesize the VHDL code 47ls165 a gate-level circuit using the Synopsys’ Class library as the target library. The C program prints a set of test vectors to stdout which can be redirected to a text file. The rest of this section describes the steps on Figure 5 for the 74LS The output file from the Test Fixturing Software can be used to make the jumper connections on the test head and to connect the timing 74lx165 pattern pods from the VXI mainframe to the test head.
74LS165 – 8-Bit Shift Register Para In/Ser Out
This can be done with 74lx165 C program or with a Perl script. However, for a more complicated circuit, the expected outputs should be generated and used for functional simulation.
All source files are included so that the reader can download the files and try to setup the test on his or her own.
For the 74LS, the Perl script topcf. The gate-level simulation uses the output file from the functional simulation as input file. The implementation is very simple and a novice VHDL designer should be able to understand.
To perform functional simulation, synthesis, and gate-level simulation with these files, the following Synopsys setup files should be used: For this example, the gate-level simulation output file is to be used for the physical test. These setup files are different from those of the CMC tutorials as a generic technology has been used for the example.
74LS – 8-Bit Shift Register Para In/Ser Out
To perform functional and gate-level simulations, the VHDL test benches lstb. In general, physical testing takes much less time than simulation in Synopsys so a more exhaustive set 744ls165 test vectors can be used for the physical test.
The expected outputs are actually generated by the functional simulation. To be able to use the test vectors for physical testing, the test vector file needs to be converted to HP PCF format.